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Si4313-B1
(AFCLimiter) which is located in register 2Ah.
AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz
The AFC Limiter register is an unsigned register and its value can be obtained from the EZRadioPRO Register
Calculator spreadsheet or from WDS.
The amount of error correction feedback to the Fractional-N PLL before the preamble is detected is controlled from
afcgearh[2:0]. The default value 000 relates to a feedback of 100% from the measured frequency error and is
advised for most applications. Every bit added will half the feedback but will require a longer preamble to settle.
The AFC operates as follows. The frequency error of the incoming signal is measured over a period of two bit
times, after which it corrects the local oscillator via the Fractional-N PLL. After this correction, some time is allowed
to settle the Fractional-N PLL to the new frequency before the next frequency error is measured. The duration of
the AFC cycle before the preamble is detected can be programmed with shwait[2:0]. It is advised to use the default
value 001, which sets the AFC cycle to 4 bit times (2 for measurement and 2 for settling).
The AFC correction value may be read from register 2Bh. The value read can be converted to kHz with the
following formula:
AFC Correction = 156.25Hz x (hbsel +1) x afc_corr[7: 0]
Frequency Correction
RX
TX
24
AFC disabled
AFC enabled
Freq Offset Register
AFC
Rev. 1.0
Freq Offset Register
Freq Offset Register
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